home
***
CD-ROM
|
disk
|
FTP
|
other
***
search
/
Atari Mega Archive 1
/
Atari Mega Archive - Volume 1.iso
/
language
/
sozobon2.zoo
/
top
/
npeep2.c
< prev
next >
Wrap
C/C++ Source or Header
|
1990-12-14
|
18KB
|
856 lines
/* Copyright (c) 1988 by Sozobon, Limited. Author: Tony Andrews
*
* Permission is granted to anyone to use this software for any purpose
* on any computer system, and to redistribute it freely, with the
* following restrictions:
* 1) No charge may be made other than reasonable charges for reproduction.
* 2) Modified versions must be clearly marked as such.
* 3) The authors are not responsible for any harmful consequences
* of using this software, even if they result from defects in it.
*/
/*
* 2-instruction peephole optimizations
*/
#include "top.h"
/*
* Macros to reference commonly-used values... cleans up the following
* code quite a bit.
*/
#define sm1 i1->src.amode /* source & dest addressing modes */
#define dm1 i1->dst.amode
#define sm2 i2->src.amode
#define dm2 i2->dst.amode
#define sr1 i1->src.areg /* source & dest registers */
#define dr1 i1->dst.areg
#define sr2 i2->src.areg
#define dr2 i2->dst.areg
/*
* ipeep2(bp, i1) - look for 2-instruction optimizations at the given inst.
*/
static int
ipeep2(bp, i1)
BLOCK *bp;
register INST *i1;
{
register INST *i2; /* the next instruction */
register INST *ti2; /* "temporary" next inst */
register int op1, op2; /* opcodes, for speed */
i2 = i1->next;
op1 = i1->opcode;
op2 = i2->opcode;
/*
* Avoid stack fix-ups after a call if possible.
*/
/*
* addq #4,sp
* ... stuff that doesn't use SP ...
* move.l ?,-(sp) => move.l ?,(sp)
*/
if (op1 == ADDQ && sm1 == IMM && i1->src.disp == 4 &&
dm1 == REG && dr1 == SP) {
ti2 = i2;
while (!uses(ti2, SP)) {
if (ti2->next == NULL)
goto end2;
ti2 = ti2->next;
}
if (ti2->opcode == MOVE && ti2->flags == LENL &&
ti2->dst.amode == (REGI|DEC) && ti2->dst.areg == SP) {
ti2->dst.amode = REGI;
delinst(bp, i1);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
}
end2:
/*
* addq #2,sp
* ... stuff that doesn't use SP ...
* move.w ?,-(sp) => move.w ?,(sp)
*/
if (op1 == ADDQ && sm1 == IMM && i1->src.disp == 2 &&
dm1 == REG && dr1 == SP) {
ti2 = i2;
while (!uses(ti2, SP)) {
if (ti2->next == NULL)
goto end3;
ti2 = ti2->next;
}
if (ti2->opcode == MOVE && ti2->flags == LENW &&
ti2->dst.amode == (REGI|DEC) && ti2->dst.areg == SP) {
ti2->dst.amode = REGI;
delinst(bp, i1);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
}
end3:
/*
* Avoid "tst" instructions following instructions that
* set the Z flag.
*/
/*
* move.x X, Y => move.x X, Y
* tst.x X or Y ...deleted...
* beq/bne beq/bne
*
* Where Y is not An, because "movea" doesn't set the
* zero flag.
*/
if (bp->last == i2 && (bp->bcode == BEQ || bp->bcode == BNE) &&
op1 == MOVE && op2 == TST &&
i1->flags == i2->flags) {
/*
* If pre-decrement is set on the dest. of the move,
* don't let that screw up the operand comparison.
*/
if (dm1 & DEC)
dm1 &= ~DEC;
if (opeq(&i1->dst, &i2->src) || opeq(&i1->src, &i2->src)) {
if (dm1 != REG || ISD(dr1)) {
delinst(bp, i2);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
}
}
/*
* and.x X, Y => and.x X, Y
* tst.x X or Y ...deleted...
* beq/bne beq/bne
*
* Where Y is not An, because "movea" doesn't set the
* zero flag.
*/
if (bp->last == i2 && (bp->bcode == BEQ || bp->bcode == BNE) &&
op1 == AND && op2 == TST &&
i1->flags == i2->flags) {
/*
* If pre-decrement is set on the dest. of the move,
* don't let that screw up the operand comparison.
*/
if (dm1 & DEC)
dm1 &= ~DEC;
if (opeq(&i1->dst, &i2->src) || opeq(&i1->src, &i2->src)) {
if (dm1 != REG || ISD(dr1)) {
delinst(bp, i2);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
}
}
/*
* ext.x Dn => ext.x Dn
* tst.x Dn ...deleted...
* beq/bne beq/bne
*
* Where Y is not An, because "movea" doesn't set the
* zero flag.
*/
if ((bp->last == i2) && (bp->bcode == BEQ || bp->bcode == BNE) &&
(op1 == EXT) && (op2 == TST) &&
(i1->flags == i2->flags)) {
if ((sm1 == REG) && ISD(sr1) && (sm2 == REG) && (sr1 == sr2)) {
delinst(bp, i2);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
}
/*
* move.? X, Dn => move.? X, Dn
* ext.? Dn ...deleted...
* beq/bne beq/bne
*
* Where Dn is dead after the "ext".
*/
if (bp->last == i2 && (bp->bcode == BEQ || bp->bcode == BNE) &&
op1 == MOVE && op2 == EXT) {
if ((dm1 == REG) && ISD(dr1) &&
(sm2 == REG) && (dr1 == sr2)) {
if ((i2->live & RM(sr2)) == 0) {
delinst(bp, i2);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
}
}
/*
* ext.l Dm => ...deleted...
* tst.l Dm tst.w Dm
*
* where Dm is dead after the "tst".
*/
if (op1 == EXT && op2 == TST &&
((i1->flags & LENL) != 0) && ((i2->flags & LENL) != 0) &&
(sr1 == sr2) && ISD(sr1)) {
if ((i2->live & RM(sr2)) == 0) {
i2->flags = LENW;
delinst(bp, i1);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
}
#if 0
/*
* add[q] #?,sp
* ... stuff that doesn't use SP ...
* unlk An => unlk An
*/
if ((op1 == ADDQ || op1 == ADD) && sm1 == IMM &&
dm1 == REG && dr1 == SP) {
ti2 = i2;
while (!uses(ti2, SP)) {
if (ti2->next == NULL)
goto end8;
ti2 = ti2->next;
}
if (ti2->opcode == UNLK) {
delinst(bp, i1);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
}
end8:
#endif
/*
* ext.l Dm => ...deleted...
* ??? N(An,Dm.l), ?? ??? N(An,Dm.w), ??
*
* Where Dm is dead
*/
if ((op1 == EXT) && (i1->flags & LENL) &&
(sm2 == (REGIDX|XLONG)) &&
(sr1 == i2->src.ireg)) {
if ((i2->live & RM(sr1)) == 0) {
sm2 &= ~XLONG;
delinst(bp, i1);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
}
/*
* ext.l Dm => ...deleted...
* ??? ??, N(An,Dm.l) ??? ??, N(An,Dm.w)
*
* Where Dm is dead
*/
if ((op1 == EXT) && (i1->flags & LENL) &&
(dm2 == (REGIDX|XLONG)) &&
(sr1 == i2->dst.ireg)) {
if ((i2->live & RM(sr1)) == 0) {
dm2 &= ~XLONG;
delinst(bp, i1);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
}
/*
* Avoid intermediate registers.
*/
/*
* move.x X, Dm => INST.x X, Dn
* INST.x Dm, Dn
*
* where Dm is dead, and INST is one of: add, sub, and, or, cmp
*/
if ((op1 == MOVE) &&
((op2==ADD)||(op2==SUB)||(op2==AND)||(op2==OR)||(op2==CMP)) &&
(i1->flags == i2->flags) &&
(dm1 == REG) && ISD(dr1) &&
(sm2 == REG) && ISD(sr2) &&
(dm2 == REG) && ISD(dr2) &&
(dr1 == sr2)) {
if ((i2->live & RM(sr2)) == 0) {
i1->opcode = i2->opcode;
dr1 = dr2;
delinst(bp, i2);
DBG(printf("%d ", __LINE__))
return DIRTY;
}
}
/*
* Silly moves
*/
/*
* move.x X, Y => move.x X, Y
* move.x Y, X
*/
if ((op1 == MOVE) && (op2 == MOVE) &&
(i1->flags == i2->flags) &&
opeq(&i1->src, &i2->dst) && opeq(&i1->dst, &i2->src) &&
((sm1 & (INC|DEC)) == 0) &&
((dm1 & (INC|DEC)) == 0)) {
delinst(bp, i2);
DBG(printf("%d ", __LINE__))
return CLEAN;
}
/*
* move.x X, Y => move.x X, Rn
* move.x Y, Rn move.x Rn, Y
*
* where Y isn't INC or DEC, and isn't register direct
*/
if ((op1 == MOVE) && (op2 == MOVE) && (dm2 == REG) &&
opeq(&i1->dst, &i2->src) && ((dm1 & (INC|DEC)) == 0) &&
(i1->flags == i2->flags) && (dm1 != REG)) {
freeop(&i1->dst);
i1->dst = i2->dst;
i2->dst = i2->src;
i2->src = i1->dst;
DBG(printf("%d ", __LINE__))
return CLEAN;
}
/*
* move.x Dm, X => move.x Dm, X
* move.x X, Y move.x Dm, Y
*
* Where 'x' is the same, and 'X' has no side-effects.
*/
if ((op1 == MOVE) && (op2 == MOVE) &&
(sm1 == REG) && ISD(sr1) &&
(i1->flags == i2->flags) && opeq(&i1->dst, &i2->src) &&
((dm1 & (DEC|IN